(a) Field of the Invention
The present invention relates to an electron emission device. More particularly, the present invention relates to an electron emission device and a manufacturing method thereof in which the electron emission device includes gate electrodes arranged on cathode electrodes with an insulation layer interposed therebetween, the gate electrodes controlling the emission of electrons from emitters.
(b) Description of the Related Art
Generally, the electron emission devices are classified into a first type where a hot cathode is used as an electron emission source and a second type where a cold cathode is used as the electron emission source. Among the second type electron emission devices there are field emitter array (FEA) types, surface conduction emitter (SCE) types, metal-insulator-metal (MIM) types, metal-insulator-semiconductor (MIS) types, and ballistic electron surface emitting (BSE) types.
The FEA type utilizes the tunneling effect of quantum mechanics to emit electrons from electron emission sources formed on cathode electrodes. The emitted electrons strike a phosphor layer formed on an anode electrode to illuminate the phosphor layer and thereby result in the display of images. The cathode electrodes, the gate electrodes, and the anode electrode form what is referred to as a triode structure. The triode structure is widely used in FEA types.
FIG. 8 is a partial sectional view of a conventional FEA types.
Cathode electrodes 3, insulation layer 5, and gate electrodes 7 are formed on backplate 1, and anode electrode 11 and phosphor layer 13 are formed on faceplate 9. Cathode electrodes 3 are formed in a stripe pattern and gate electrodes 7 are formed in a stripe pattern such that cathode electrodes 3 intersect gate electrodes 7 substantially perpendicular. First and second openings 5a and 7a are formed respectively in insulation layer 5 and gate electrodes 7 corresponding to where cathode electrodes 3 and gate electrodes 7 intersect. Emitters 15, which act as electron emission sources, are formed on surfaces of cathode electrodes 3 exposed by first and second openings 5a and 7a. 
Such emitters 15 are formed by performing deposition through a thick-layer process (e.g., screen printing) using a carbon-based material such as carbon nanotubes or graphite, after which baking is performed. Compared to Spindt-type emitters, manufacture is simple and the resulting emitters are more suitable for use in devices of large screen sizes.
However, when material for forming emitters 15 is deposited on cathode electrodes 3 using a thick-layer process, it is possible for the conductive emitter material to be inadvertently formed extending from cathode electrodes 3 to gate electrodes 7 to thereby form a short circuit between these two elements. Therefore, a sacrificial layer is used in the formation of emitters 15 to thereby prevent the formation of short circuits.
FIGS. 9a-9d are partial sectional views used to describe the processes involved in forming emitters in the production of the conventional FEA types.
Referring first to FIG. 9a, cathode electrodes 3, insulation layer 5, and gate electrodes 7 are formed in this sequence on backplate 1. Next, first and second openings 5a and 7a are formed respectively in and passing fully through insulation layer 5 and gate electrodes 7 at areas corresponding to where cathode electrodes 3 and gate electrodes 7 intersect. Backplate 1 is made of a transparent glass substrate, and cathode electrodes 3 are made of a transparent conducting film having a high transmissivity of light such as ITO (indium tin oxide).
Subsequently, except for specific areas of cathode electrodes 3 (i.e., areas exposed by first and second openings 5a and 7a), sacrificial layer 17 is formed over all exposed areas of gate electrodes 7, insulation layer 5, and cathode electrodes 3. Sacrificial layer 17 is made of a conventional photoresist material or a metal.
Next, with reference to FIG. 9b, paste-like emitter material 19 is deposited using a thick-layer process over all exposed elements formed on backplate 1, that is, over sacrificial layer 17 and the exposed portions of cathode electrodes 3. Next, ultraviolet rays (depicted by dark arrows) are irradiated onto a surface of backplate 1 opposite the side on which the above elements are formed to thereby selectively harden emitter material 19 on cathode electrodes 3.
Following the above processes, with reference to FIG. 9c, emitter material 19 that has not been hardened is removed. Baking is then performed to thereby complete the formation of emitters 15. Next, etching is performed using an etching solution to remove sacrificial layer 17 as shown in FIG. 9d. This completes the formation of the structure present on backplate 1.
However, there is a serious problem with the configuration realized through the processes described above. In particular, the etching solution used to remove sacrificial layer 17 may damage gate electrodes 7. Gate electrodes 7 are typically made of a thin metal having a thickness of approximately 200 nm. The cross-sectional area of gate electrodes 7 is reduced by damage to the surface of gate electrodes 7 by the etching solution. This results in an increase in the line resistance of gate electrodes 7 and/or cracking of the gate electrodes when emitter material 19 is baked.
When predetermined drive voltage are applied to cathode electrodes 3 and gate electrodes 7 to effect the emission of electrons from emitters 15 (in this increased state of resistance of gate electrodes 7), the voltage applied to gate electrodes 7 is reduced. Ultimately, this results in a non-uniform emission of electrons from emitters 15 which significantly reduces overall picture quality.